SK Hynix Aims to Double Wafer Capacity

According to Reuters, SK Group chairman Chey Tae-won told reporters at Computex in Taipei that SK Hynix "is going to double the whole capacity over the next five years," a statement Reuters reported with a direct quote. Tom's Hardware and Bloomberg report Chey repeated a prior forecast that the AI-driven memory shortage could persist until 2030. Reuters cites Counterpoint Research figures showing SK Hynix holding about 58% of the global HBM market in the first quarter. Tom's Hardware reports Chey declined to provide an exact buildout cost but said 2026 capital spending would climb well above 30.2 trillion won the company spent in 2025, and Tom's Hardware additionally reports Chey confirmed SK Hynix has filed to list American depositary receipts in New York this year.

Industry-pattern observations: Public reporting highlights HBM (high-bandwidth memory) as the immediate driver of wafer demand because HBM consumes many more wafers per bit than commodity DRAM, raising wafer-equivalent demand even when bit-volume growth is moderate. Tom's Hardware describes HBM as a high-margin product that has skewed capacity allocation within the industry toward advanced packaging and HBM production lines. Tom's Hardware notes a greenfield fab lead time of more than five years, a timing point that places new capacity near the tail end of the shortage window Chey cited.

Editorial analysis: For practitioners and infrastructure planners, the announcement reinforces two linked trends seen across multiple industry reports. First, concentration of HBM production among a few suppliers, here cited at 58% for SK Hynix by Counterpoint Research per Reuters, increases the fragility of supply for AI accelerators. Second, long lead times and capital intensity for memory fabs mean near-term relief is limited, even when large expansions are announced. Bloomberg and Strait Times coverage underline that volatile inputs such as land, equipment, and electricity complicate precise capex estimates and extend uncertainty around the timing of additional output.

Observers should monitor a small set of measurable indicators that will determine when wafer supply materially eases. Key items to track are:

• •Quarterly HBM shipment and wafer-start data from suppliers and industry trackers such as Counterpoint Research and TrendForce
• •Reported capital expenditure and fab construction milestones, including permits and equipment orders noted in filings or trade press
• •DRAM and HBM contract-price trajectories, since sharp price increases affect both hyperscaler procurement and supplier margins

For practitioners: watch supplier share shifts in HBM and announced partnerships or subcontracting in Taiwan and elsewhere, as Tom's Hardware reports SK Hynix is seeking additional manufacturing partnerships beyond TSMC. Analysts and procurement teams should also factor multi-year timing into capacity planning for AI clusters because lead times for wafer-scale additions typically exceed two to five years.

What is reported in these sources is the chairman's public statement and industry data points; none of the scraped sources include a company-released, line-item capex plan with project timelines. Where the chairman's remarks are paraphrased rather than quoted, articles attribute the statements to reporters' on-site coverage. SK Hynix has not released a detailed, itemized public schedule in the scraped reporting cited here.