Google Engages Samsung for Icefish TPU Component

The Information reports that Alphabet's Google is in talks with Samsung Electronics to have Samsung manufacture part of its next-generation tensor processing unit, codenamed "Icefish." Reuters reports that Google plans for TSMC to fabricate the main compute die while Samsung would produce a memory-facing I/O die using its 2-nanometer process. Reuters and TrendForce report that the Icefish program is being developed with chip designer MediaTek and that mass production is being eyed as early as 2028. Reuters also reports Google has separately discussed large-volume TPU manufacturing with Intel. Reuters notes Samsung declined to comment and that Alphabet did not immediately respond to requests for comment.

High-performance AI accelerators typically divide functionality across a high-density compute die and companion dies or packages that handle memory interfaces, power management, and I/O. Using a leading-edge node for an I/O or HBM-adjacent die is unusual but not unprecedented when a vendor can integrate advanced packaging and memory expertise. Reports that Samsung could supply HBM, the I/O die, and advanced packaging are consistent with vertically integrated offers other vendors have pitched to hyperscalers.

Public reporting frames these negotiations as part of a broader push by cloud and chip customers to reduce single-supplier concentration, because TSMC is approaching full utilization from surging AI demand. Suppliers with both memory and foundry capabilities, and with packaging ecosystems, can present turnkey value to large AI chip buyers. TrendForce and other trade outlets highlight Samsung's recent wins, including a reported $16.5 billion order from Tesla, as background for its foundry momentum.

Observers will track three indicators:

• •whether Google publicly confirms a split supply chain and the specific dies allocated to each foundry
• •qualification timelines and packaging demonstrations that show Samsung can meet Google's HBM and interposer specs at scale
• •capacity ramp schedules for Samsung's Texas fab and TSMC's 1.4-nanometer programs as cited in trade reporting

Additional confirmations from Google partners such as MediaTek or from contract announcements would materially raise confidence in the reported arrangement.

If multi-supplier manufacturing for large AI accelerators becomes more common, engineering teams should expect greater heterogeneity in packaging, thermal behavior, and supply-chain traceability. Systems teams and performance engineers will likely need earlier co-validation of packaging and memory subsystems when dies originate from different fabs.