Google Seeks Samsung Capacity for Next-Gen TPU

The Information reports that Google is in advanced talks with Samsung Electronics to manufacture a component of its tenth-generation Tensor Processing Unit, codenamed Icefish. Under the reported split-manufacturing plan, TSMC would produce the primary compute die on its upcoming 1.4-nanometer process, while Samsung would make a separate memory-interface component using 2-nanometer Gate-All-Around technology. Google is also working with chip designer MediaTek on the project, with mass production targeted for as early as 2028. Alphabet shares fell approximately 1.9% on the report. The arrangement, if confirmed, would mark a meaningful foundry win for Samsung and a shift in Google's historically TSMC-only TPU supply chain.
What happened
The Information reports Google is in advanced talks with Samsung Electronics to produce part of its tenth-generation Tensor Processing Unit (TPU), codenamed Icefish. Under the reported arrangement, TSMC would manufacture the primary compute die on its upcoming 1.4-nanometer process, while Samsung would produce a separate memory-interface component using 2-nanometer Gate-All-Around technology. Google is also working with Taiwanese chip designer MediaTek on the project. The chip is targeted for mass production as early as 2028, though the timeline remains subject to change. Alphabet shares fell approximately 1.9% following the report.
Why split manufacturing
Google has historically relied on TSMC for its TPUs, but TSMC faces surging demand from Nvidia and other AI chip buyers, tightening advanced-node allocation for large customers. At the same time, Google's AI chips are attracting more external customers, increasing production volume requirements. A split-die approach lets Google use Samsung's 2nm capacity for the memory-interface component while keeping the most performance-critical compute logic on TSMC's 1.4nm node.
What it means for Samsung
Winning a component role in Google's next-generation TPU would be a significant foundry achievement for Samsung, which has been competing with TSMC in advanced logic. Samsung has recently secured manufacturing contracts with Tesla (AI6 chip) and Nvidia (language processing unit for the Vera Rubin platform), and an Icefish component win would add a high-profile hyperscaler AI workload to its foundry portfolio.
Technical context
Process node labels such as 2nm and 1.4nm refer to generations of chip manufacturing technology. Smaller nodes generally enable higher transistor density, improving performance and power efficiency. Google's reported split-die design separates the highest-density compute logic from the memory-interface component, allowing different process optimizations for each part.
Caveats
Google and Samsung have not publicly confirmed the arrangement. Production volumes, contractual terms, and yield expectations have not been disclosed. The 2028 mass-production target is conditional on development progress. Observers should treat these as reported negotiations rather than confirmed plans.
Scoring Rationale
A reported Google-Samsung split-manufacturing arrangement for next-gen TPUs is notable for AI hardware supply chains and foundry competition, directly relevant to cloud infrastructure and procurement planning. Primary source is The Information (paywalled); arrangement unconfirmed publicly, so notable rather than major.
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