Qualcomm unveils HBC near-memory architecture for data centers

Qualcomm unveiled High Bandwidth Compute (HBC) at its June 24, 2026 Investor Day, presenting it as a near-memory, 3D-stacked architecture that places a logic accelerator beneath an LPDDR memory stack, per Qualcomm's Investor Day materials reported by BusinessWire and Wccftech. Reporting by Wccftech includes numerical claims from the presentation that HBC delivers a 6x increase in bandwidth per watt compared with HBM, and a 200x capacity-per-watt improvement versus SRAM; those claims are attributed to Qualcomm's presentation as covered by Wccftech. Wccftech describes the physical implementation as an HBC accelerator bonded to LPDDR using TSVs and mounted on a shared 2D organic substrate in the first-generation design; ServeTheHome's coverage emphasizes system-level design, 3D integration, and ecosystem details.

Wccftech places HBC inside Qualcomm's broader Dragonfly data-center roadmap, where the AI250 accelerator is the first chip to ship with HBC Gen1; Wccftech reports the AI250-based card will offer 133 TB/s of bandwidth per card and an 18x uplift versus prior AI200 LPDDR5X configurations. BusinessWire describes the Dragonfly portfolio as including the Dragonfly C1000 CPU and the Dragonfly AI300 accelerator on the multi-generation roadmap. ServeTheHome's live coverage includes on-the-ground detail about Qualcomm emphasizing system-level design, 3D integration, LPDDR scale, and power-efficiency IP during Investor Day.

Editorial analysis: For practitioners, HBC represents a near-memory architecture variant that swaps conventional HBM stacks for larger-capacity LPDDR coupled closely to logic, prioritizing capacity and energy per token over raw HBM peak bandwidth. Industry reporting frames this choice as targeting inference workloads at hyperscaler scale, where larger model footprints and token throughput raise energy and total-cost-of-ownership concerns (Reuters; BusinessWire). Reuters additionally reports that Microsoft and Meta have signed on to use Qualcomm's new chips, and that Qualcomm projects $15 billion in data-center chip sales by 2029 with $5 billion in fiscal 2027 revenue guidance, statements attributed to Reuters coverage of the Investor Day and comments by CFO Akash Palkhiwala.

Editorial analysis: For engineers and architects, HBC's stated tradeoff-using LPDDR with near-memory compute-suggests a different optimization surface than HBM-centric accelerators. Comparable near-memory or in-package compute approaches historically improve effective bandwidth and energy per operation for memory-bound kernels, but they also change thermal, routing, and packaging requirements. Observed patterns in similar transitions: adoption at hyperscaler scale typically depends on validated performance/watt per real-world inference workloads and on supply-chain readiness for TSV bonding and assembly, as the ServeTheHome coverage emphasizes Qualcomm's partner ecosystem claims.

• •Product timelines and availability, where Wccftech reports HBC Gen1 on AI250 targeted for mid-2027 and a Gen2 HBC with the AI300 accelerator aimed at 2028. These schedule claims come from the Investor Day presentation as reported.
• •Independent benchmarks versus HBM-based accelerators and end-to-end power-per-token measurements reported by customers or third parties, which will determine whether HBC's claimed 6x bandwidth-per-watt advantage holds on production workloads (Wccftech reporting of Qualcomm claims).
• •Integration and supply-chain indicators, including reported multi-year deals and ecosystem support referenced in BusinessWire and Reuters, and whether those translate into production deployments at scale.

Editorial analysis: For practitioners evaluating architecture choices, the HBC announcement highlights an active industry tradeoff space between raw peak bandwidth (HBM) and large-capacity, energy-efficient near-memory designs. Observers should treat Qualcomm's numeric claims as vendor-reported until independent validation and third-party benchmarks appear.