NVIDIA Reportedly Reduces Vera Rubin Memory Configuration
On July 26, Wccftech reported that NVIDIA may halve the CPU-side LPDDR5X memory planned for Vera Rubin NVL72 systems, citing GF Securities. TrendForce had separately reported a supply-driven SOCAMM reduction in June, while NVIDIA's public specifications still list 54TB of CPU memory per rack. The reports concern host memory, not the listed 20.7TB of HBM4 attached to Rubin GPUs.
NVIDIA may reduce the CPU-side LPDDR5X memory planned for its Vera Rubin NVL72 rack-scale AI system, according to reports from TrendForce and Wccftech. The change has not appeared in NVIDIA's public specifications, which still list 54TB of LPDDR5X CPU memory and 20.7TB of GPU-side HBM4 per rack.
What the reports say
TrendForce reported on June 10 that NVIDIA had decided to halve the SOCAMM memory capacity of Vera Rubin Superchip modules. The research firm described the change as a response to limited LPDRAM allocation under suppliers' preliminary 2027 production plans, not a reduction in NVIDIA's overall memory demand.
On July 26, Wccftech cited a GF Securities analysis that put the revised SOCAMM module capacity at 96GB instead of 192GB. The same analysis projected 28TB of Vera CPU memory per NVL72 rack rather than the 54TB to 55TB previously expected. It said the rack's 20.7TB of HBM4 would remain unchanged because the reported cut affects CPU-side LPDDR5X.
NVIDIA's current Vera Rubin product page still lists 1.5TB of LPDDR5X per Vera CPU and 54TB across an NVL72 rack. The company labels the specifications preliminary and subject to change. That leaves the analyst reports useful for planning, but not equivalent to a final NVIDIA configuration announcement.
HBM4 keeps cost pressure high
Wccftech also cited a separate Bernstein estimate that a Vera Rubin NVL72 rack could cost $9.1 million if HBM4 reaches $53 per GB in 2027. The outlet contrasted that with an earlier $7.8 million rack estimate based on lower memory-price assumptions.
These are analyst estimates rather than NVIDIA-published prices or bills of materials. They depend on future HBM4 and LPDDR5X pricing, supplier allocation, and the final shipping configuration. The distinction also matters technically: reducing host memory can lower rack cost and stretch LPDDR5X supply, but it does not reduce the HBM4 capacity directly available to the Rubin GPUs under the reported plan.
What infrastructure teams should track
For buyers, the reports show why rack-level cost models should separate GPU HBM, CPU memory, networking, power, and cooling instead of treating accelerator price as the whole system cost. Host-memory reductions could also affect workloads that rely on CPU-side data staging, model orchestration, or memory offload, although the available reporting does not quantify any performance effect.
Procurement teams should therefore model the reported 28TB configuration as a scenario, not a confirmed specification. The most important next evidence will be an updated NVIDIA datasheet, partner shipping configuration, or final pricing that confirms whether the public 54TB figure changes.
Key Points
- 1TrendForce and Wccftech reported a supply-driven reduction in Vera Rubin's CPU-side SOCAMM memory, while NVIDIA's public specifications still list 54TB per NVL72 rack.
- 2The reported cut affects LPDDR5X host memory; the listed 20.7TB of GPU-side HBM4 remains unchanged in the GF Securities scenario.
- 3Bernstein's reported $9.1 million rack estimate depends on future HBM4 pricing and is not an NVIDIA-published price.
Scoring Rationale
The reported memory change could affect rack configuration and infrastructure cost planning for NVIDIA's next-generation platform. The current public NVIDIA specification has not changed, so the analyst reports remain consequential but unconfirmed.
Sources
Primary source and supporting public references used for this report.
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