Marvell Wins Google TPUv8e Networking Chip

Wccftech reports, citing Funda AI and tipster Jukan, that Marvell has been tapped to design a custom networking chip for Google's TPUv8e. The article says the part is likely to be manufactured on Intel's 18A or 18AP process and is expected to enter volume production by the end of 2027, per the same report. Wccftech also reports that MediaTek is involved in the ASIC I/O and back-end design while Intel would handle fabrication and EMIB-based packaging. The piece frames this as another commercial win for Marvell and references prior public praise of Marvell by NVIDIA's CEO, though the article does not include a verbatim quote.
What happened
Wccftech reports, citing Funda AI and tipster Jukan, that Marvell has been tasked to design a custom networking chip for Google's TPUv8e accelerators. The article says the networking ASIC is likely to be produced on Intel's 18A or 18AP process and that the design is expected to reach volume production by the end of 2027, per the same report. Wccftech further reports that MediaTek is handling I/O and back-end design for the ASIC while Intel would provide fabrication and EMIB-based packaging. The article also references recent praise of Marvell by NVIDIA's CEO, but it does not supply a verbatim quote.
Technical details
Editorial analysis - technical context: Networking ASICs for large-scale accelerators coordinate data flow, congestion management, and synchronization across device clusters. For practitioners, moving such a chip to Intel's 18A/18AP node would imply targeting high bandwidth, integration with advanced packaging like EMIB, and tight latency/telemetry constraints. These are general technical pressures seen across hyperscaler custom silicon programs and are not assertions about internal engineering choices at Google beyond what Wccftech reports.
Context and significance
Industry context: Public reporting of a custom networking ASIC for TPUv8e aligns with a broader industry pattern where hyperscalers pair bespoke compute dies with equally bespoke I/O and networking silicon to reduce system-level latency and improve utilization. A contract awarded to Marvell, if confirmed, would be consistent with the company's increasing footprint in data-center networking and AI-infrastructure supply chains. That said, the current report is sourced to Funda AI and a tipster via Wccftech, and it appears not to be corroborated by a public Google, Marvell, Intel, or MediaTek disclosure in the scraped sources.
What to watch
Look for primary confirmations from the companies involved or supply-chain filings. Key indicators include product briefs, packaging photos, foundry or packaging partner announcements, and trade filings that reference volume-production timelines or process nodes. Observers should also check for corroboration from additional industry press or official statements before treating the production timeline and process node as settled.
Scoring Rationale
The report describes a potentially important infrastructure contract that would affect accelerator networking design and supply chains. Impact is limited by reliance on a single, tip-based report and absence of direct confirmations from Google, Marvell, Intel, or MediaTek.
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