Marvell Wins Google TPUv8e Networking Chip
Wccftech reports, citing Funda AI and tipster Jukan, that Marvell has been tapped to design a custom networking chip for Google's next-generation TPUv8e accelerator, reportedly codenamed Humufish. The part is likely to be built on Intel's 18A or 18AP process and to reach volume production by the end of 2027, per the report, with MediaTek handling I/O and back-end design and Intel providing fabrication and EMIB-based packaging while Google designs the main compute die. The specific chip claim remains tip-based and is not confirmed by Google, Marvell, Intel, or MediaTek. However, independent outlets including The Next Web and Fudzilla have reported that Google is working with Marvell on custom AI inference silicon within a multi-partner TPU supply chain that also includes Broadcom and MediaTek, lending broader support to the direction even if the exact networking-chip details are unconfirmed.
What happened
Wccftech reports, citing Funda AI and tipster Jukan, that Marvell has been tasked with designing a custom networking chip for Google's TPUv8e accelerator, reportedly codenamed Humufish. The networking ASIC is likely to be produced on Intel's 18A or 18AP process and to reach volume production by the end of 2027, per the report. Wccftech further reports that MediaTek would handle I/O and back-end design while Intel provides fabrication and EMIB-based packaging, with Google designing the main compute die. The report references recent public praise of Marvell by NVIDIA's CEO but does not supply a verbatim quote.
Sourcing and corroboration
The specific networking-chip claim is tip-based, sourced to Funda AI and a tipster via Wccftech, and is not confirmed by Google, Marvell, Intel, or MediaTek. Independent outlets provide partial corroboration of the broader direction: The Next Web reported Google is in talks with Marvell to build custom AI inference chips as part of a multi-partner supply chain that also includes Broadcom and MediaTek, and Fudzilla reported Google is tapping Marvell for TPU networking. Treat the exact process node and 2027 timeline as unconfirmed pending primary disclosure.
Technical context
Networking ASICs for large accelerator clusters coordinate data movement, congestion management, and synchronization across many devices. Building such a part on a leading-edge node with advanced packaging like EMIB implies an emphasis on bandwidth, latency, and tight integration. These are general engineering pressures common to hyperscaler custom-silicon programs, not confirmed internal choices at Google beyond what is reported.
Why it matters
A networking-chip win would extend Marvell's footprint in data-center and AI-infrastructure silicon and fits an industry pattern in which hyperscalers pair bespoke compute dies with custom I/O and networking parts to cut system-level bottlenecks and raise utilization. The reported use of Intel foundry and packaging would also be a notable external-customer signal for Intel's 18A program, if confirmed.
What to watch
- •Primary confirmations from Google, Marvell, Intel, or MediaTek, or supply-chain filings referencing the program.
- •Product briefs, packaging disclosures, or foundry announcements that name a process node or production timeline.
- •Additional independent corroboration before treating the node and schedule as settled.
Key Points
- 1Wccftech reports Google has tapped Marvell to design a custom networking ASIC for the TPUv8e, citing Funda AI and tipster Jukan; the specific claim is unconfirmed by the named companies.
- 2The reported use of Intel 18A/18AP and EMIB-based packaging, with MediaTek on I/O and back-end design, points to a bandwidth- and integration-focused design for hyperscaler accelerators.
- 3Independent reporting (The Next Web, Fudzilla) that Google is working with Marvell on custom inference silicon corroborates the broader multi-partner TPU supply-chain direction, even where chip-level specifics remain tip-based.
Scoring Rationale
A potentially important hyperscaler infrastructure development affecting accelerator networking and the Intel/Marvell/MediaTek supply chain, now partly corroborated by independent reporting that Google is working with Marvell on custom inference silicon. The score is held just below the higher infrastructure tier because the specific networking-chip, process-node, and 2027 timeline claims remain tip-based and unconfirmed by the named companies.
Sources
Public references used for this report.
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