Intel unveils Clearwater Xeon 6+ with 288 cores

Intel introduced the Clearwater Forest data-center family, announced as the Xeon 6+ series, with chips supporting up to 288 E-cores, built on its 18A (2nm-class) process, per DataCenterDynamics. DataCenterDynamics reports a 17 percent Instructions Per Cycle (IPC) uplift versus the prior generation. The outlet also reports Intel has declared its Fab 52 in Chandler, Arizona, fully operational and able to mass-produce Intel 18A parts. The Register provides additional architecture detail, saying the design uses twelve 24-core tiles fabbed on 18A stacked above three tiles on Intel 3 that house memory controllers and L3 cache, with PCIe, CXL, and accelerators on two I/O dies borrowed from earlier Xeon parts.

Editorial analysis - technical context: High core counts are achieved by combining a stripped-down core microarchitecture with advanced packaging and process scaling. According to The Register, Clearwater uses Intel's smaller Darkmont E-cores rather than higher-clocked P-cores, and those E-cores lack AVX-512, AMX, and hardware hyperthreading. DataCenterDynamics reports Intel characterises 18A as delivering up to 15 percent better performance-per-watt and 30 percent improved chip density, and names PowerVia and RibbonFET as enabling technologies.

Public reporting frames Clearwater as part of Intel's density-and-efficiency push for hyperscalers, telcos, and cloud providers. For AI/agentic workflows that generate many small, CPU-bound tasks (retrieval, API orchestration, tool invocation, code execution, and light-weight model runtimes), very high socket-level core counts can reduce contention and latency across concurrent threads. At the same time, reporting notes a trade-off: cores that drop wide-vector and matrix extensions are less suitable for heavy FP or large-model inference workloads that benefit from AVX/AMX or dedicated accelerators. The Register highlights that reuse of existing I/O dies and socket compatibility should ease OEM integration.

For practitioners: monitor how cloud providers price and expose high-core-count instances built on Clearwater, and whether orchestration frameworks and agent runtimes are optimised to exploit many smaller cores. Also watch comparisons of throughput-per-dollar and energy-per-task versus GPU- and accelerator-backed instances for end-to-end agent workloads. Reporting includes a direct quote from Intel CEO Lip-Bu Tan: "We are entering an exciting new era of computing, made possible by great leaps forward in semiconductor technology that will shape the future for decades to come." DataCenterDynamics attributes that quote to Intel.