TSMC Reports 98% CoWoS Yield at 5.5x Reticle

CoWoS, or Chip-on-Wafer-on-Substrate, is TSMC's family of advanced-packaging technologies for integrating large logic dies and high-bandwidth memory in a single package. The 5.5x designation refers to package scale relative to the lithography reticle limit, the maximum area exposed in one lithographic step.

TrendForce reports that TSMC expects a 14x-reticle CoWoS package to enter production in 2028, followed by packages beyond 14x in 2029. The same report says a 14x package could integrate roughly 10 large compute dies and 20 HBM stacks. TSMC's North America Technology Symposium roadmap, reported by Tom's Hardware in April, described packages of 14 reticles and above, with up to 24 HBM5E stacks, by 2029.

The differing publication dates and roadmap descriptions leave the precise 2028-2029 sequencing unclear. The common point in the reporting is that TSMC is extending package-scale integration far beyond earlier CoWoS roadmaps that topped out at 9.5 reticles, according to Tom's Hardware.

For accelerator designers, increasing package area can create room for more compute chiplets and HBM stacks without requiring one monolithic die beyond reticle limits. Industry work on comparable multi-die systems, however, treats package yield as only one production variable: memory availability, substrate supply, thermal behavior, power delivery, test coverage, and system-level reliability can each constrain shipment volumes.

He said TSMC had nearly doubled CoWoS capacity annually over the previous three years and operated 10 advanced-packaging facilities, according to TrendForce. He added, "We haven't fully met demand yet, but we're getting very close."

He also identified memory and Ajinomoto build-up film, or ABF, substrates as AI supply-chain bottlenecks, TrendForce reported. That distinction matters because a mature interposer and assembly flow does not remove constraints in the surrounding bill of materials. HBM stack availability and substrate lead times can limit final accelerator output even when packaging yields improve.

TSMC also discussed its System-on-Integrated-Chips, or SoIC, hybrid-bonding roadmap. TrendForce, citing TechNews, reported that SoIC pitch reached 6 microns in 2025 and is targeted to narrow to 4.5 microns by 2029. The report also cited TSMC's previously stated availability target for A14-to-A14 SoIC production in 2029, with 1.8x higher die-to-die I/O density than N2-on-N2 SoIC.

The reported CoWoS yield is therefore a useful indicator of manufacturing maturity at a large package scale, but it is not a standalone measure of available AI compute. For ML infrastructure teams, the near-term relevance remains tied to accelerator supply, memory configurations, and the packaging choices made by GPU and custom-silicon vendors.