Imec demonstrates 3D CCD memory architecture

Per presentations and documentation shown at the 2026 IEEE International Memory Workshop, imec demonstrated the first functional three-dimensional implementation of a charge-coupled device (CCD) intended for memory applications, according to EEJournal, New Electronics, and Dataconomy. The demonstrator uses an indium gallium zinc oxide (IGZO) channel and a vertical string architecture formed by drilling memory holes through a stack of three word-lines that act as phase gates, per EEJournal and New Electronics. Imec reported charge transfer across the gates at speeds exceeding 4 MHz, as noted by EEJournal, New Electronics, and Dataconomy. The device implements serial, charge-based storage and block-level access rather than the byte-addressable model used by conventional DRAM, Dataconomy and New Electronics report. Reporting by imec and outlets describes processing the CCD in a 3D NAND-like, punch-and-plug flow and frames the architecture as a candidate for CXL type-3 buffer memory to serve multiple processors through a high-bandwidth switch.

Per EEJournal and New Electronics, the functional 3D CCD demonstrator comprises vertical memory strings routed through three phase-gate word-lines and transfers charge along an IGZO channel using pulsed voltages. The stack demonstrated is limited to a small number of layers in the prototype, EEJournal reports, but the fabrication approach is compatible with 3D NAND-style stacking and the associated cost structure. Dataconomy and imec materials note the design trades byte-addressability for block-level transfers, making it more similar operationally to NAND-type devices than to DRAM.

Editorial analysis: The memory industry has been exploring alternatives to conventional DRAM and high-bandwidth memory as model sizes and parallel processors drive demand for larger, cheaper pools of shared memory. Devices designed as CXL type-3 buffers are intended to provide large block-level pools accessible to multiple accelerators; public reporting frames imec's 3D CCD as targeting that niche. Comparable research tracks in the sector evaluate technologies that can combine high bit density with acceptable latency for streaming large blocks to GPUs and accelerators.

Editorial analysis: For systems architects and ML infrastructure teams, a block-addressable, high-density buffer memory changes tradeoffs in memory hierarchy design. New device classes that prioritize cost per bit and endurance over single-cycle byte access typically require software and interconnect adaptations, such as larger DMA windows and block-oriented prefetching. Observers should view the 3D CCD as a potential new tier in the memory stack rather than a drop-in DRAM replacement.

Editorial analysis: Key near-term indicators include demonstrations of larger stack counts beyond the three-word-line prototype, published endurance and retention numbers under AI-like workloads, detailed CXL interoperability tests, and manufacturing yield data demonstrating compatibility with 3D NAND process flows. Industry uptake will depend on whether vendors can integrate block-oriented buffers into accelerator memory maps and on how quickly the CXL ecosystem standardizes such use cases.

Per multiple outlets and imec materials, the 3D CCD demonstrator shows technical feasibility for a block-addressable, high-bit-density buffer built with an IGZO channel and vertical NAND-like stacking, and it achieved transfer speeds above 4 MHz in the prototype. Broader impact will hinge on scaling, manufacturing economics, endurance metrics, and systems-level integration into CXL-based memory pools.