Huawei-led team completes post-training of DeepSeek 1.6T model
A Huawei-led research team completed full-parameter post-training of DeepSeek's V4-Pro, a 1.6-trillion-parameter model, on a cluster of at least 1,000 Huawei Ascend 910C chips, according to a Shenzhen government announcement reported by the South China Morning Post and Tom's Hardware. SCMP reports the run updated every model weight rather than using adapter layers and completed more than 1,500 training iterations without interruption while improving the model's mathematical performance. Tom's Hardware cites DeepSeek documentation placing V4-Pro's pre-training corpus above 32 trillion tokens. The collaboration included Huawei, the Shenzhen Loop Area Institute, the Shenzhen campus of Harbin Institute of Technology, and the Shenzhen Institute of Big Data. Tom's Hardware cautions the result does not show Ascend chips can pre-train a frontier model from scratch.
What happened
A Huawei-led research team says it completed full-parameter post-training of DeepSeek's V4-Pro, a 1.6-trillion-parameter model, on a cluster of at least 1,000 Huawei Ascend 910C chips, according to a Shenzhen government announcement reported by the South China Morning Post and Tom's Hardware.
The technical claim
Per SCMP, the team ran full-parameter post-training - updating every weight rather than relying on adapter layers - and completed more than 1,500 training iterations without a single interruption or error, while improving the model's mathematical performance. Tom's Hardware cites DeepSeek documentation placing V4-Pro's pre-training corpus above 32 trillion tokens.
Who was involved
SCMP and Tom's Hardware report the effort brought together Huawei, the Shenzhen Loop Area Institute, the Shenzhen campus of Harbin Institute of Technology, and the Shenzhen Institute of Big Data.
Why it matters
Domestic post-training at this scale advances China's push toward semiconductor self-reliance amid tightening US export controls, moving Ascend silicon from inference toward training-class workloads and reducing reliance on foreign accelerators for alignment and tuning.
What it does not show
As Tom's Hardware notes, completing post-training on Ascend hardware does not demonstrate the chips can pre-train a frontier model from scratch, which remains a heavier technical and cost hurdle. Reproducible wall-clock, power, and throughput data would be the next signals of practical parity.
Scoring Rationale
A reported full-parameter post-training of a 1.6-trillion-parameter model on a 1,000-chip Ascend 910C cluster is a strategically significant infrastructure milestone, corroborated by SCMP and Tom's Hardware and tied to China's drive for semiconductor self-reliance under US export controls. It matters to practitioners weighing domestic compute options but stops short of demonstrating frontier-scale pre-training parity.
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