Fubon Projects 12 Million to 15 Million Google TPU v9 Chips by 2028

Tom's Hardware reported that Fubon's note describes TPU v9 as using four compute dies per processor. The note says the generation could more than double Google's associated capacity consumption in 2028 compared with 2027.

A multi-die accelerator depends on advanced packaging and high-bandwidth interconnects to combine its compute components. TechSpot reported that Fubon sees manufacturing capacity as a potential constraint and considers Intel Foundry a possible supplementary supplier if TSMC alone cannot meet the projected volume. That remains an analyst view rather than a confirmed Google sourcing plan.

Packaging choices also are not interchangeable. Designs built around Intel's EMIB technologies and TSMC's CoWoS-L approach have different physical and engineering requirements, so a second manufacturing route would require product-specific planning rather than a simple transfer of the same package.

The projection compares the number of Google-designed TPUs deployed by one hyperscaler with Nvidia accelerators sold across cloud providers, enterprises, and system vendors. It does not establish equivalent performance, market share, or delivered compute. Architecture, memory bandwidth, networking, numerical formats, software support, and workload mix all affect usable training and inference capacity.

For ML infrastructure teams, the useful signal is the possible scale of custom-silicon demand. If the forecast proves accurate, advanced packaging and foundry capacity would become central constraints on Google's 2028 accelerator build-out. Until Google provides a roadmap or production guidance, however, the 12 million to 15 million figure should be treated as a reported analyst projection rather than a committed deployment target.