Broadcom Adds FuriosaAI for Custom AI Accelerators

Broadcom has added FuriosaAI to its list of partners building AI accelerators that leverage Broadcom's packaging and networking technology, The Register reports. According to The Register, FuriosaAI claims its third-generation processor will be fabricated on 2nm process nodes and will use "dual layer" HBM4 or HBM4e memory made possible by Broadcom's advanced packaging. The Register further reports FuriosaAI plans to use Broadcom's Ethernet and PCIe products to support systems exceeding eight chips, which implies the use of high-radix switches such as Broadcom's Tomahawk 6 (TH6). The Register frames this collaboration alongside Broadcom's 3.5D XDSiP packaging approach, which assembles disaggregated chiplets using 3D bonding techniques.

Multi-die system-in-package approaches, like the 3.5D XDSiP described by The Register, reduce the need to design monolithic SoCs by enabling separate chiplets for compute, memory, and I/O. Industry-pattern observations: companies pursuing chiplet-based accelerators commonly target advanced packaging plus high-bandwidth memory to trade integration complexity for faster time-to-market and modular scalability. Hybrid bonding and stacked HBM variants are central to achieving the high memory bandwidth required for inference-heavy workloads, while Ethernet-based fabrics are increasingly considered for scaling beyond a single package.

Industry-pattern observations: Broadcom's packaging and switch portfolio has become a glue layer for multiple AI hardware stacks, according to public coverage. The Register's mention of AMD tunneling over Ethernet, and OEMs using Broadcom TH6 switches, highlights an industry trend where Ethernet is being explored as a viable alternative to proprietary scale-up interconnects like NVLink for certain deployments. For practitioners, that shifts some system-level design trade-offs toward standard networking technologies and off-the-shelf switch silicon.