AMD Confirms Ryzen AI Max 400 Supports 192GB

VideoCardz reports that a presentation slide for the Ryzen AI Max 400 family, codenamed "Gorgon Halo", shows support for up to 192GB of unified memory and up to 160GB allocatable as VRAM. VideoCardz's slide also lists up to 16 Zen 5 CPU cores (32 threads), up to 5.2 GHz CPU boost, up to 40 RDNA 3.5 GPU compute units, and 55 TOPS for the XDNA 2 NPU. Tom's Hardware frames the chips as a modest refresh of the existing Strix Halo lineup and notes pre-orders for Ryzen AI Halo systems opening in June, starting at $3,999. Leaks reported by Wccftech and igor'sLAB add PassMark entries and clock/benchmark details for the flagship MAX+ 495, including reported single- and multi-core scores and upgraded Radeon 8065S graphics.
What happened
VideoCardz reports that AMD's Ryzen AI Max 400 family, codenamed "Gorgon Halo", will support up to 192GB of unified memory and allow up to 160GB to be allocated as VRAM, based on an AMD presentation slide summarized by VideoCardz. VideoCardz's slide also lists configurations with up to 16 Zen 5 CPU cores / 32 threads, CPU boost clocks up to 5.2 GHz, up to 40 RDNA 3.5 GPU compute units with GPU boost up to 3.0 GHz on some SKUs, and 55 TOPS from the XDNA 2 NPU.
Tom's Hardware reports the Gorgon Halo chips are a minor refresh of the earlier Strix Halo (Ryzen AI Max 300) family and quotes availability timing and pricing for associated systems, stating pre-orders for Ryzen AI Halo systems with Strix Halo will open in June starting at $3,999. Wccftech and igor'sLAB circulated leaks and PassMark listings for the flagship MAX+ 495 that include reported benchmark numbers and an upgraded integrated Radeon 8065S GPU.
Technical details / Editorial analysis - technical context
Per the aggregated reporting, the Ryzen AI Max 400 family retains the same architectural mix seen in prior Halo APUs, Zen 5 CPU cores, an RDNA-derived integrated GPU generation reported as RDNA 3.5, and an XDNA 2 neural engine. The most consequential change in the slides and leaks is the higher unified memory ceiling: 192GB unified LPDDR5x is materially larger than the 128GB ceiling on Strix Halo systems reported earlier. Industry observers and the outlets reporting the leaks note modest clock bumps (for example, a 100 MHz boost on the flagship MAX+ 495 vs prior Halo parts) rather than wholesale architectural changes.
Industry context:
For ML practitioners, a unified memory pool that scales toward 192GB with up to 160GB usable as VRAM can materially change on-device model capacity and batching options for large language models and other memory-heavy workloads. Observed patterns in comparable mobile and laptop SoC advances show that increases in unified memory capacity often translate into better on-device inference for bigger models or higher-resolution data, reducing dependence on external accelerators for some workflows. However, Tom's Hardware flags supply-side headwinds: public reporting notes global DRAM tightness, which can affect the practical availability and pricing of high-memory SKUs.
What to watch
- •Confirmed availability and configuration list from AMD or OEMs; outlets report pre-orders for Halo systems opening in June, according to Tom's Hardware.
- •Real-world memory allocation behavior and software support: whether frameworks (PyTorch, TensorFlow, ROCm) and model runtimes can meaningfully expose larger unified memory to GPU/NPU inference.
- •Effective NPU performance and software stack maturity: the slide lists 55 TOPS for XDNA 2, but measured throughput, precision modes, and tooling will determine usability for production ML workloads.
Editorial analysis: If the marketed memory and NPU upgrades arrive in volume, the generation will be a practical option for workstation-class on-device ML development and inference where energy, latency, or data locality matter. Observers should track availability and pricing, because higher memory SKUs are most useful when software and thermals allow consistent allocation to GPU/NPU workloads.
Scoring Rationale
A higher unified-memory ceiling and modest compute upgrades make this a notable hardware development for practitioners who run models locally, but it is an incremental refresh rather than a platform paradigm shift.
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