Spiking Neuron Enables On-Chip Machine Learning
On Dec. 3, 2025, Steven Louis et al. present LTspice simulations of a CMOS+X spiking neuron combining an NMOS transistor with a magnetic tunnel junction (MTJ). The NMOS+MTJ reproduces threshold spiking, latency, refractory periods, synaptic integration, inhibition, and adaptation, and enables on-chip spike-timing-dependent gradient-descent learning in analog multilayer networks, showing reliable training on a nonlinear task and potential for low-power, in-memory edge neuromorphic hardware.
Key Points
- 1Demonstrates NMOS+MTJ neuron reproducing spiking, latency, refractory periods, synaptic integration, inhibition, and adaptation
- 2Implements spike-timing-dependent, gradient-descent weight updates enabling analog-domain training and inference
- 3Suggests feasible path to compact, low-power, in-memory neuromorphic hardware for edge applications
Scoring Rationale
Novel NMOS+MTJ analog learning demonstrates practical neuromorphic direction, but remains simulation-only without fabricated validation or benchmarking.
Sources
Public references used for this report.
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