SiFive launches P570 Gen3 RVA23-compliant RISC-V core

SiFive announced the Performance P570 Gen 3, an out-of-order 64-bit RISC-V core compliant with the RVA23 ISA profile, aimed at edge AI, high-end consumer, and commercial IoT devices, according to the company's press release distributed via Business Wire (reported by Las Vegas Sun). The core uses a 3-wide, 13-stage fully out-of-order pipeline, a 128-bit VLEN vector pipeline with dot-product extensions, and is scalable to up to 16 cores in a core complex, per SiFive's announcement and reporting by CNX-Software. SiFive's release cites workload benchmarks: 7-13% SpecInt gains and a 13% dynamic power reduction versus the P550 Gen1, plus up to 2X Geekbench and up to 21X improvements on specific AI workloads, as reported by Business Wire and CNX-Software. Krste Asanovic is quoted in the press release on the core's RVA23 support and efficiency.
What happened
According to SiFive's press release distributed via Business Wire and reporting by CNX-Software, SiFive launched the Performance P570 Gen 3 64-bit out-of-order RISC-V core that is compliant with the RVA23 ISA profile. The announcement states the core targets edge AI, high-end consumer, and commercial IoT applications running rich operating systems such as Android and enterprise Linux distributions. The company release and CNX-Software report that the core implements a 3-wide, 13-stage fully out-of-order superscalar pipeline, a single 128-bit VLEN vector pipeline with dot-product extensions, and scalability up to 16 cores in a compute subsystem.
Technical details
According to the press materials and CNX-Software, the P570 Gen 3 supports all mandatory RVA23 profile extensions and adds multiple optional extensions including Smepmp, Zvkng, Zvksg, Zicfilp, Zicfiss, Zfbfmin, Zvfbfmin, Zvfbfwma, and Zvdot4a8i. The announcement cites benchmark figures: 7-13% combined improvement on SpecInt 2006/2017 versus the P550 Gen1, a 13% reduction in dynamic power (mW/GHz) relative to P550, and a 2X uplift in Geekbench for CPU workloads with up to 21X gains on select AI-relevant workloads-benchmarks and comparative claims are presented in the press release and CNX-Software coverage. The release also describes companion system IP including a RISC-V standard-compliant advanced interrupt architecture (AIA), a second-generation RISC-V standard-compliant IOMMU, and WorldGuard security primitives.
Industry context
Editorial analysis: Vendors building high-performance RISC-V cores are increasingly prioritizing RVA23 compatibility and expanded vector units to make RISC-V viable for mainstream OSes and edge AI inference. The emphasis on 128-bit vector pipelines and dot-product instructions mirrors a broader supplier trend of pushing specialized ISA extensions to accelerate convolution and matrix-multiply workloads on-device.
For practitioners
Editorial analysis: Hardware and firmware engineers integrating next-generation SoCs should note reported scalability (up to 16 cores) and the explicit RVA23 support, which, if implemented as advertised, reduces the integration work required to run modern Android builds and enterprise Linux. Systems teams evaluating on-device inference should treat vendor benchmark claims as starting points and plan independent benchmarking for targeted workloads, power envelopes, and thermal constraints.
What to watch
For practitioners: follow upstream kernel and firmware support (distribution of the RVA23 extension set into mainstream toolchains), availability of OP-TEE support being upstreamed (reported collaboration with RISCstar and RISE by CNX-Software), silicon tapeouts or partner SoC announcements that pair P570 Gen 3 with GPUs (Imagination Technologies is mentioned in the press text), and independent performance and power measurements across representative AI inference workloads.
Scoring Rationale
This is a notable architecture and IP release from a leading RISC-V vendor that advances vector performance and RVA23 support, which matters to system architects and engineers targeting edge AI and consumer devices. The story is important but not a paradigm shift.
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