Rebellions Unveils Rebel 100 Chiplet Accelerator
Rebellions detailed its Rebel 100 quad-chiplet AI accelerator at ISSCC 2026, using UCIe-Advanced die-to-die interconnects to stitch four NPUs into a single 2 FP8 PFLOPS (1 FP16 PFLOPS) SiP rated at 600W. Each 320 mm2 NPU die pairs with a 12‑Hi HBM3E 36 GB stack (144 GB per package), a mesh NoC, and aggregated 4 TB/s UCIe bandwidth with ~11 ns FDI latency. The design targets large-model inference scale and rack-level deployment.
Key Points
- 1Implements UCIe-A to link four NPUs yielding 4 TB/s aggregated bandwidth and 11ns latency
- 2Uses 12‑Hi HBM3E per chiplet and mesh NoC to support 2 FP8 PFLOPS inference
- 3Enables scale-up/out clusters for trillion-parameter models with simplified software-visible single‑processor semantics
Scoring Rationale
Strong technical novelty and broad hardware implications, tempered by vendor-provided performance figures lacking independent verification.
Sources
Public references used for this report.
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