Google Splits TPU 8 Into Training and Inference Chips

Google introduced its eighth-generation TPU family at Google Cloud Next on April 22, 2026, as two purpose-built chips: TPU 8t for training and TPU 8i for inference, replacing the single-architecture approach of prior generations. Both chips are, for the first time, paired with Google's own Axion Arm-based CPU hosts rather than third-party x86 hosts, and both were designed in partnership with Google DeepMind to match evolving agentic model architectures. Google says both chips will be generally available later in 2026. Industry analysts, notably SemiAnalysis, have reported that TPU 8t (pre-launch codename Sunfish) is co-designed with Broadcom and TPU 8i (pre-launch codename Zebrafish) is co-designed with MediaTek; Google's own announcement does not name silicon design partners.

TPU 8t is built for scale: a single superpod reaches 9,600 chips and two petabytes of shared high-bandwidth memory, delivering 121 exaflops of compute and roughly 3x the per-pod compute performance of the prior generation, Ironwood. Google says it targets over 97% goodput, the share of time a cluster spends on productive training rather than recovering from faults, through real-time telemetry, automatic rerouting around failed interconnect links, and optical circuit switching that reconfigures hardware without human intervention. TPU 8i is tuned for latency: it pairs 288GB of high-bandwidth memory with 384MB of on-chip SRAM, three times the on-chip memory of the previous generation, doubles interconnect bandwidth to 19.2 terabits per second, and uses a new Boardfly network topology intended to keep chained, multi-agent inference calls fast. Google says TPU 8i delivers 80% better performance-per-dollar than Ironwood. Both chips are fabricated on TSMC's 2-nanometer process, per industry reporting, and use fourth-generation liquid cooling.

The split means training and inference clusters will diverge architecturally in ways that affect procurement and software, not just hardware: TPU 8t nodes will be denser in HBM and interconnect for large-scale distributed training under JAX and Pathways, while TPU 8i nodes prioritize on-chip memory and low-latency collectives for serving chained agent calls, with support for JAX, MaxText, PyTorch, SGLang, and vLLM. Because Google has not officially named its ASIC design partners, teams evaluating supply risk should treat the Broadcom-training, MediaTek-inference split as well-corroborated but unofficial, and watch TSMC 2nm and CoWoS/HBM packaging capacity as the likely near-term bottleneck given competing demand from Nvidia and other custom-silicon programs.

• •December 2025: Early industry reports described Google's next-generation TPU split under leaked codenames and noted MediaTek reserving TSMC CoWoS packaging capacity for the project.
• •April 7, 2026: Pre-announcement analyst coverage referred to the training and inference chips by the codenames Sunfish and Zebrafish.
• •April 22, 2026: Google officially unveiled the chips as TPU 8t and TPU 8i at Google Cloud Next 2026.

Whether Google confirms its silicon design partners directly rather than leaving the Broadcom/MediaTek split to analyst reporting; how CoWoS and HBM packaging capacity gets allocated across Google, Nvidia, and other ASIC customers as TPU 8t and 8i ramp toward their stated later-2026 general availability; and whether real-world benchmarks validate Google's claimed 3x training and 80% inference price-performance gains once early customers, including Citadel Securities, report results.