Google Reportedly Selects Intel EMIB For TPUv8e

Wccftech reports that Google's next-generation TPU, described in coverage as TPUv8e, will reportedly be manufactured at Intel Foundry using Intel's EMIB (embedded multi-die interconnect bridge) advanced packaging, citing a Taiwanese supply-chain outlet. Wccftech also reports that Intel Foundry has secured Tesla as a large customer for its 14A process. The article states that Google's prior AI chips used TSMC's CoWoS packaging and that, per reporting, MediaTek is responsible for the I/O and back-end design on TPUv8e while a separate TPU variant, TPUv8p, is reported to rely on Broadcom and TSMC's CoWoS/SoCI packaging.

Editorial analysis - technical context: EMIB is Intel's embedded multi-die interconnect bridge packaging approach, which routes high-density interconnects between dies via small embedded bridges. In industry comparisons, CoWoS (Chip-on-Wafer-on-Substrate) is a widely used 2.5D packaging method from TSMC that integrates multiple dies on an interposer. Reported tradeoffs between EMIB and CoWoS in public coverage centre on cost, scalability, and design flexibility; these are general engineering considerations rather than claims about the companies' internal design rationales.

Coverage framing places this report inside a broader narrative of foundry and packaging competition, where cloud providers and AI chip designers seek alternatives to dominant suppliers. Wccftech's mention of a Tesla win for Intel Foundry on 14A is presented as evidence of recent customer traction for Intel Foundry, per that outlet's reporting. If the reported sourcing is later confirmed, it would be one more public example of hyperscalers diversifying packaging and foundry partners, but that implication is an industry-level observation and not a documented statement from Google or Intel.

For practitioners: look for official confirmations from Google, Intel Foundry, or the named vendors; published packaging tech briefs or datasheets that specify EMIB use; and reporting on yields, thermal and signal integrity benchmarks for any EMIB-based TPU samples. Also monitor whether additional supply-chain disclosures identify wafer fabs, test-and-assembly locations, and timeline estimates for production ramp, since packaging choices materially affect cost, latency, and integration workflows.