Delos Data unveils rack-scale platform for startups

Per The Register, Delos Data, a startup founded by former Intel and Barefoot Networks executives, showed a modular server reference design at Computex intended to simplify rack-scale integration for AI accelerators. The Register reports the chassis front contains 36 OSFP cages, each capable of 1.6 Tbps, arranged as nine cages per one of four OAM sockets. Using a 200 Gbps SerDes assumption, The Register calculates about 3.6 TB/s of interconnect per chip, a number it compares to Nvidia's Rubin GPUs. The Register also highlights that a GB300 NVL72 requires 18 400 Gbps ports per GPU, illustrating the large port counts rack-scale designs demand.

Per The Register, the use of OSFP means the chassis can accept standard DACs or pluggable transceivers and can carry Ethernet or alternative fabrics such as UALink or PCIe over the same physical interfaces. The design emphasizes dense external I/O and open accelerator module (OAM) sockets rather than a proprietary backplane.

Editorial analysis: Companies building rack-scale AI systems face two linked systems problems: an order-of-magnitude growth in external interconnect bandwidth per accelerator, and corresponding mechanical, power, and cooling integration. Public reporting frames Delos Data's offering as an attempt to modularize the physical and networking plumbing so chip designers can avoid building custom racks from scratch. EE Times coverage of Majestic Labs, which raised $100 million for a memory-pooling server design, shows a complementary trend where system suppliers focus on disaggregation and novel packaging to address memory and bandwidth constraints.

Editorial analysis: Observers and engineers should note that achieving rack-scale performance increasingly depends on system-level choices outside the chip: socket form factors (OAM), pluggable optics (OSFP), SerDes speed, and how fabrics are mapped across modules. Delos Data's approach, as reported by The Register, leans on standardized high-density I/O to let accelerators plug into existing fabric choices rather than forcing a proprietary interconnect.

Editorial analysis: Watch for interoperability details (supported protocol stacks over OSFP), vendor support for OAM modules, and whether other hyperscalers or system vendors publish compatible reference designs. Also track alternative system architectures such as the memory-pooled designs reported by EE Times, which address the related but distinct bottleneck of memory capacity and bandwidth.