China proposes 14nm logic–18nm DRAM 3D-bonded AI chip claiming Nvidia-class performance, aiming independence
At the ICC Global CEO Summit, China Semiconductor Industry Association vice chairman Wei Shaojun announced a domestically designed AI processor that pairs 14nm logic with 18nm DRAM using 3D hybrid bonding and software-defined near‑memory compute. He claimed the design achieves 2 TFLOPS/W and 120 TFLOPS total throughput—performance he says rivals Nvidia’s latest chips—while enabling a fully domestic supply chain to reduce dependence on CUDA and Western vendors. Wei gave few technical details and did not present independent benchmarks, leaving questions about thermal management, yields, and software ecosystem support. He said fuller disclosures will follow later this year as China pursues architecture-and-packaging-led competitiveness instead of node scaling.
Key Points
- 1Core technical detail: 14nm logic stacked with 18nm DRAM via 3D hybrid bonding to enable near‑memory compute, claimed 120 TFLOPS at 2 TFLOPS/W.
- 2Business implication: The design is pitched as a route to decouple China from Nvidia/CUDA and U.S. export constraints by building a domestic hardware and software stack.
- 3Future impact: If validated, the approach could shift competitive emphasis from node scaling to advanced packaging and system architecture, but adoption depends on thermal/yield realities and broad software/tooling support.
Sources
Public references used for this report.
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