AMD Taps GlobalFoundries for MI500 Co-packaged Optics
AMD is partnering with GlobalFoundries to manufacture the Photonic Integrated Circuits for its MRM Co-packaged Optic (CPO) solution that will accompany the next-generation Instinct MI500 AI accelerators. ASE will handle packaging, while AMD will continue to source the MI500 compute dies from TSMC on an advanced 2nm node and pair them with CDNA 6 architecture and HBM4E memory. The MI500 family targets a substantial AI performance uplift and higher memory bandwidth than the MI400's 19.6TB/s. NVIDIA is pursuing a parallel CPO route using TSMC for PICs and SPIL for packaging, underscoring a broader industry pivot to silicon photonics to reduce interconnect latency and enable higher rack-scale bandwidth for large-scale AI training and inference.
What happened
AMD is building a Co-packaged Optics (CPO) stack for its next-generation Instinct MI500 accelerators, and it has engaged GlobalFoundries to manufacture the Photonic Integrated Circuits (PICs) for an MRM-based CPO solution. ASE is slated to perform packaging, while AMD will source the MI500 compute dies from TSMC on an advanced 2nm process and deploy the CDNA 6 architecture with HBM4E memory, targeting bandwidth above 19.6TB/s achieved by the MI400 family.
Technical details
The announced split of responsibilities isolates PIC fabrication from chip fabrication and packaging. Key participants and roles are:
- •GlobalFoundries for PIC manufacturing
- •ASE for photonic-electronic packaging
- •TSMC for MI500 compute die fabrication
- •NVIDIA parallels this approach with TSMC PICs, SPIL packaging, and final assembly by Foxconn Industrial Internet
The CPO approach locates high-speed photonic interfaces adjacent to accelerator silicon to shorten optical-electrical paths, reduce latency, and enable substantially higher aggregate interconnect bandwidth at rack and pod scale. AMD's choice of an MRM (micro-ring modulator) photonics approach targets dense wavelength-division multiplexing and compact PIC layouts compatible with high-port-count switch fabrics.
Context and significance
The AMD-GlobalFoundries tie-up is a clear industry signal that major accelerator vendors are moving beyond copper and near-package optics to true co-packaged optics for next-generation AI factories. With both AMD and NVIDIA racing to integrate CPO, the industry is converging on solutions that prioritize link density, power efficiency per bit, and reduced serialization latency for large distributed training workloads. For system builders and data center operators, CPO adoption will reframe rack design, thermal budgets, and optics supply chains.
What to watch
Execution risks remain in yield, thermal integration, and standardization of PIC interfaces across vendors. Monitor early MI500 system demos, bandwidth-per-port claims, and packaging yield metrics from ASE and GlobalFoundries to assess how quickly CPO moves from prototype to production deployments.
Scoring Rationale
This is a notable infrastructure development: a major accelerator vendor coordinating photonics fabrication and packaging with established foundries. It advances co-packaged optics from lab prototypes toward production, affecting data center interconnect design and supply chains.
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