AMD Introduces Versal Gen 2 Memory-on-Package SoC

According to AMD's blog post, AMD announced the Versal Premium Gen 2 Memory on Package adaptive SoCs that integrate up to 32 GB of LPDDR5X on-package and provide up to 288 GB/s of memory bandwidth. AMD's announcement states the MoP parts reduce board area by up to 60% compared with discrete LPDDR5X designs and are designed for 15-plus-year lifecycles; the blog also notes integrated hard IP for PCIe 6.0 and CXL 3.1. ServeTheHome and Videocardz.com report that the shift away from on-package HBM toward LPDDR5X is being framed in public coverage as a response to constrained HBM supply and rising HBM pricing.

Per AMD's published materials and reporting from StorageReview and Videocardz.com, MoP devices begin sampling at the end of 2026 with production shipments expected in the second half of 2027. Standard AMD Versal Premium Series Gen 2 devices (without MoP) are already shipping now and can be used for development today.

Industry-pattern observations: Memory-on-package is distinct from traditional package-on-board approaches and from HBM stacks. MoP with LPDDR5X places multiple low-power DRAM dies in the same package substrate rather than using an HBM interposer stack. Compared with HBM, LPDDR5X typically trades peak bandwidth and power characteristics for lower cost, broader supplier availability, and simpler thermal/board handling. AMD's product documentation and the Versal Gen 2 product guide list configurable AI engine and PL resources for the family; AMD's blog highlights target use cases including test and measurement, professional video, VPX secure-communications and compact telecom deployments where board area and lifecycle matter.

AMD's blog post includes a quoted line from Sumit Shah, head of product management and marketing for the Adaptive and Embedded Computing Group, saying, "Our customers can design for the system they want to build, not the one their memory constraints allow, and bring it to market faster." The announcement claims MoP implementations will enable designers to avoid board-level memory validation and simulation work by shipping pre-validated on-package memory. Videocardz.com reports that Versal Gen 2 MoP can use up to four LPDDR5X ICs at speeds up to 9,000 MT/s, enabling the stated 288 GB/s aggregate bandwidth.

Reporting places AMD's move alongside similar choices in the semiconductor ecosystem where suppliers trade HBM's peak-density advantages for broader supply and cost stability. ServeTheHome frames the launch as a notable shift for AMD's programmable-logic business following prior HBM-equipped Versal and Xilinx products. Observers covering infrastructure and edge compute will see this as an example of vendors optimizing for supply-chain and lifecycle constraints while preserving usable bandwidth for inference, video, and network-acceleration workloads.

Monitor vendor support for thermal and signal-integrity reference designs for MoP parts, partner ecosystem readiness for LPDDR5X on-package modules, and qualifier metrics such as sustained bandwidth under real inference workloads. Also watch whether other FPGA/SoC vendors announce MoP variants or new packaging partnerships as HBM supply dynamics evolve, and track sampling and production timeline milestones against AMD's stated late-2026 and 2027 targets.